{
  "schema_version": 1,
  "design": "first-order continuous-time 1-bit ADC + CIC2 R256",
  "clock_Hz": 1000000.0,
  "output_rate_Hz": 3906.25,
  "nominal_supply_V": 1.8,
  "output_bits": 8,
  "nominal_LSB_V": 0.00703125,
  "effective_resolution": "measured independently; never inferred from code width",
  "source_sha256": {
    "workers/eda/sigma_delta.py": "f093720df75b1223fbadeb1d7b71c4a41087bc271fc03c5f59d94cb290d3d8a7",
    "workers/eda/rtl/sigma_delta8.v": "06033a7a9d84f2cf0c43a73c30ba489626d02a515cb5f5decbf3bf908febb42c",
    "workers/eda/rtl/sigma_delta8_gate.v": "5792a1a31a3275518b544cd5a0c69a08d161bf82526e6111fe90a469e5112eb9",
    "workers/eda/rtl/sigma_delta8_cmos.json": "b2eaed1744483b63883404fde9090c14e0b04dacbb0ebce1b9f175cd2ca83900"
  },
  "blocks": [
    {
      "id": "sdm8_input_filter",
      "name": "\u03a3\u0394 \u00b7 \uc785\ub825 RC anti-alias \ud544\ud130",
      "ports": [
        "VIN",
        "OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [],
      "all_child_cells": [],
      "primitive_counts": {
        "resistor": 1,
        "capacitor": 1
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_input_filter.json",
      "spice": "spice/sdm8_input_filter.spice",
      "project_bundle": "projects/sdm8_input_filter.register.zip"
    },
    {
      "id": "sdm8_reference",
      "name": "\u03a3\u0394 \u00b7 VDD/2 \uae30\uc900\uc804\uc555 \u00b7 \ub514\ucee4\ud50c\ub9c1",
      "ports": [
        "VCM",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [],
      "all_child_cells": [],
      "primitive_counts": {
        "resistor": 2,
        "capacitor": 1
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_reference.json",
      "spice": "spice/sdm8_reference.spice",
      "project_bundle": "projects/sdm8_reference.register.zip"
    },
    {
      "id": "sdm8_bias",
      "name": "\u03a3\u0394 \u00b7 \uc800\ud56d\u00b7\ub2e4\uc774\uc624\ub4dc MOS \ubc14\uc774\uc5b4\uc2a4",
      "ports": [
        "BIAS",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [],
      "all_child_cells": [],
      "primitive_counts": {
        "resistor": 1,
        "nmos": 1
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_bias.json",
      "spice": "spice/sdm8_bias.spice",
      "project_bundle": "projects/sdm8_bias.register.zip"
    },
    {
      "id": "sdm8_ota",
      "name": "\u03a3\u0394 \u00b7 7-MOS 2\ub2e8 Miller OTA",
      "ports": [
        "INP",
        "INN",
        "BIAS",
        "OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "SDM8_OTA_FIRST"
      ],
      "all_child_cells": [
        "SDM8_OTA_FIRST"
      ],
      "primitive_counts": {
        "nmos": 4,
        "pmos": 3,
        "capacitor": 1,
        "resistor": 1
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_ota.json",
      "spice": "spice/sdm8_ota.spice",
      "project_bundle": "projects/sdm8_ota.register.zip"
    },
    {
      "id": "sdm8_integrator",
      "name": "\u03a3\u0394 \u00b7 \ud569\uc0b0 \uc800\ud56d \u00b7 \ud53c\ub4dc\ubc31 \uc801\ubd84\uae30",
      "ports": [
        "VIN",
        "DACB",
        "VCM",
        "BIAS",
        "OUT",
        "RESET",
        "RESETB",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "SDM8_OTA",
        "SDM8_RESET_SWITCH"
      ],
      "all_child_cells": [
        "SDM8_OTA",
        "SDM8_OTA_FIRST",
        "SDM8_RESET_SWITCH"
      ],
      "primitive_counts": {
        "nmos": 6,
        "pmos": 5,
        "capacitor": 2,
        "resistor": 3
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_integrator.json",
      "spice": "spice/sdm8_integrator.spice",
      "project_bundle": "projects/sdm8_integrator.register.zip"
    },
    {
      "id": "sdm8_comparator",
      "name": "\u03a3\u0394 \u00b7 7-MOS 1\ube44\ud2b8 \ube44\uad50\uae30",
      "ports": [
        "INP",
        "INN",
        "BIAS",
        "OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "PREAMP"
      ],
      "all_child_cells": [
        "PREAMP"
      ],
      "primitive_counts": {
        "nmos": 4,
        "pmos": 3
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_comparator.json",
      "spice": "spice/sdm8_comparator.spice",
      "project_bundle": "projects/sdm8_comparator.register.zip"
    },
    {
      "id": "sdm8_sample_latch",
      "name": "\u03a3\u0394 \u00b7 \uc0d8\ud50c DFF \u00b7 reset MUX",
      "ports": [
        "D",
        "CLK",
        "RESET",
        "Q",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "MUX2",
        "DFF"
      ],
      "all_child_cells": [
        "MUX2",
        "INV",
        "DFF"
      ],
      "primitive_counts": {
        "pmos": 12,
        "nmos": 12
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_sample_latch.json",
      "spice": "spice/sdm8_sample_latch.spice",
      "project_bundle": "projects/sdm8_sample_latch.register.zip"
    },
    {
      "id": "sdm8_dac",
      "name": "\u03a3\u0394 \u00b7 1\ube44\ud2b8 NRZ \ud53c\ub4dc\ubc31 DAC",
      "ports": [
        "BITSTREAM",
        "DACB",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "INV"
      ],
      "all_child_cells": [
        "INV"
      ],
      "primitive_counts": {
        "pmos": 1,
        "nmos": 1
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_dac.json",
      "spice": "spice/sdm8_dac.spice",
      "project_bundle": "projects/sdm8_dac.register.zip"
    },
    {
      "id": "sdm8_clock_buffer",
      "name": "\u03a3\u0394 \u00b7 2\ub2e8 \ud074\ub85d \ubc84\ud37c",
      "ports": [
        "CLK",
        "CLK_OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "INV",
        "INV"
      ],
      "all_child_cells": [
        "INV"
      ],
      "primitive_counts": {
        "pmos": 2,
        "nmos": 2
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_clock_buffer.json",
      "spice": "spice/sdm8_clock_buffer.spice",
      "project_bundle": "projects/sdm8_clock_buffer.register.zip"
    },
    {
      "id": "sdm8_reset_switch",
      "name": "\u03a3\u0394 \u00b7 \uc801\ubd84\uae30 \ucd08\uae30\ud654 \uc804\uc1a1 \uac8c\uc774\ud2b8",
      "ports": [
        "RESET",
        "RESETB",
        "VCM",
        "SUM",
        "OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [],
      "all_child_cells": [],
      "primitive_counts": {
        "nmos": 2,
        "pmos": 2
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_reset_switch.json",
      "spice": "spice/sdm8_reset_switch.spice",
      "project_bundle": "projects/sdm8_reset_switch.register.zip"
    },
    {
      "id": "sdm8_modulator",
      "name": "\u03a3\u0394 \u00b7 1\ucc28 \uc544\ub0a0\ub85c\uadf8 \uc2dc\uadf8\ub9c8\ub378\ud0c0 \ubaa8\ub4c8\ub808\uc774\ud130",
      "ports": [
        "VIN",
        "CLK",
        "RESET",
        "BITSTREAM",
        "VCM",
        "BIAS",
        "INT_OUT",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "SDM8_INPUT_FILTER",
        "SDM8_REFERENCE",
        "SDM8_BIAS",
        "SDM8_CLOCK_BUFFER",
        "INV",
        "SDM8_INTEGRATOR",
        "SDM8_COMPARATOR",
        "SDM8_SAMPLE_LATCH",
        "SDM8_DAC"
      ],
      "all_child_cells": [
        "SDM8_INPUT_FILTER",
        "SDM8_REFERENCE",
        "SDM8_BIAS",
        "SDM8_CLOCK_BUFFER",
        "INV",
        "SDM8_INTEGRATOR",
        "SDM8_OTA",
        "SDM8_OTA_FIRST",
        "SDM8_RESET_SWITCH",
        "SDM8_COMPARATOR",
        "PREAMP",
        "SDM8_SAMPLE_LATCH",
        "MUX2",
        "DFF",
        "SDM8_DAC"
      ],
      "primitive_counts": {
        "resistor": 7,
        "capacitor": 4,
        "nmos": 27,
        "pmos": 24
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_modulator.json",
      "spice": "spice/sdm8_modulator.spice",
      "project_bundle": "projects/sdm8_modulator.register.zip"
    },
    {
      "id": "sdm8_reset_sync",
      "name": "\u03a3\u0394 \u00b7 \ub9ac\uc14b \ud574\uc81c 2FF \ub3d9\uae30\ud654",
      "ports": [
        "CLK",
        "RESET",
        "RESET_INTERNAL",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "OR2",
        "DFF_N",
        "DFF_N"
      ],
      "all_child_cells": [
        "OR2",
        "NOR2",
        "INV",
        "DFF_N",
        "DFF"
      ],
      "primitive_counts": {
        "pmos": 23,
        "nmos": 23
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_reset_sync.json",
      "spice": "spice/sdm8_reset_sync.spice",
      "project_bundle": "projects/sdm8_reset_sync.register.zip"
    },
    {
      "id": "sdm8_frame_counter",
      "name": "\u03a3\u0394 \u00b7 256 \uc0d8\ud50c \ud504\ub808\uc784 \uce74\uc6b4\ud130",
      "ports": [
        "CLK",
        "RESET",
        "LAST_SAMPLE",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
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        "INV",
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        "INV",
        "INV",
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        "OR2",
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        "OR2",
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        "AND2",
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        "AND2",
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        "INV",
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        "AND2",
        "AND2",
        "AND2",
        "INV",
        "OR2",
        "AND2",
        "AND2",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N"
      ],
      "all_child_cells": [
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        "OR2",
        "NOR2",
        "AND2",
        "NAND2",
        "DFF_N",
        "DFF"
      ],
      "primitive_counts": {
        "pmos": 189,
        "nmos": 189
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_frame_counter.json",
      "spice": "spice/sdm8_frame_counter.spice",
      "project_bundle": "projects/sdm8_frame_counter.register.zip"
    },
    {
      "id": "sdm8_cic_integrators",
      "name": "\u03a3\u0394 \u00b7 17\ube44\ud2b8 CIC \uc801\ubd84\uae30 2\ub2e8",
      "ports": [
        "CLK",
        "RESET",
        "BIT_IN",
        "NEXT_SUM0",
        "NEXT_SUM1",
        "NEXT_SUM2",
        "NEXT_SUM3",
        "NEXT_SUM4",
        "NEXT_SUM5",
        "NEXT_SUM6",
        "NEXT_SUM7",
        "NEXT_SUM8",
        "NEXT_SUM9",
        "NEXT_SUM10",
        "NEXT_SUM11",
        "NEXT_SUM12",
        "NEXT_SUM13",
        "NEXT_SUM14",
        "NEXT_SUM15",
        "NEXT_SUM16",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
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        "AND2",
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        "AND2",
        "AND2",
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        "DFF_N",
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        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N",
        "DFF_N"
      ],
      "all_child_cells": [
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        "AND2",
        "NAND2",
        "XOR2",
        "OR2",
        "NOR2",
        "DFF_N",
        "DFF"
      ],
      "primitive_counts": {
        "pmos": 1038,
        "nmos": 1038
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_cic_integrators.json",
      "spice": "spice/sdm8_cic_integrators.spice",
      "project_bundle": "projects/sdm8_cic_integrators.register.zip"
    },
    {
      "id": "sdm8_cic_combs",
      "name": "\u03a3\u0394 \u00b7 17\ube44\ud2b8 CIC comb 2\ub2e8",
      "ports": [
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        "RESET",
        "ENABLE",
        "SUM0",
        "SUM1",
        "SUM2",
        "SUM3",
        "SUM4",
        "SUM5",
        "SUM6",
        "SUM7",
        "SUM8",
        "SUM9",
        "SUM10",
        "SUM11",
        "SUM12",
        "SUM13",
        "SUM14",
        "SUM15",
        "SUM16",
        "FILTERED0",
        "FILTERED1",
        "FILTERED2",
        "FILTERED3",
        "FILTERED4",
        "FILTERED5",
        "FILTERED6",
        "FILTERED7",
        "FILTERED8",
        "FILTERED9",
        "FILTERED10",
        "FILTERED11",
        "FILTERED12",
        "FILTERED13",
        "FILTERED14",
        "FILTERED15",
        "FILTERED16",
        "VPWR",
        "VGND"
      ],
      "direct_dependencies": [
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "INV",
        "AND2",
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        "AND2",
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        "XOR2",
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        "OR2",
        "AND2",
        "XOR2",
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        "INV",
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        "OR2",
        "AND2",
        "AND2",
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        "AND2",
        "OR2",
        "XOR2",
        "INV",
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        "OR2",
        "XOR2",
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        "XOR2",
        "INV",
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        "OR2",
        "AND2",
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        "AND2",
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        "XOR2",
        "INV",
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        "AND2",
        "AND2",
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      ],
      "all_child_cells": [
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      ],
      "primitive_counts": {
        "pmos": 1515,
        "nmos": 1515
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
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      "spice": "spice/sdm8_cic_combs.spice",
      "project_bundle": "projects/sdm8_cic_combs.register.zip"
    },
    {
      "id": "sdm8_scale_saturate",
      "name": "\u03a3\u0394 \u00b7 8\ube44\ud2b8 \uc2a4\ucf00\uc77c \u00b7 \ud3ec\ud654 \ucc98\ub9ac",
      "ports": [
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        "VGND"
      ],
      "direct_dependencies": [
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        "OR2",
        "OR2",
        "OR2",
        "OR2"
      ],
      "all_child_cells": [
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      ],
      "primitive_counts": {
        "pmos": 24,
        "nmos": 24
      },
      "layout_status": "not-generated",
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      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sdm8_scale_saturate.json",
      "spice": "spice/sdm8_scale_saturate.spice",
      "project_bundle": "projects/sdm8_scale_saturate.register.zip"
    },
    {
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      "name": "\u03a3\u0394 \u00b7 8\ube44\ud2b8 \ucd9c\ub825 \ub808\uc9c0\uc2a4\ud130 \u00b7 VALID",
      "ports": [
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        "ENABLE",
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        "CODE_IN1",
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        "CODE_IN3",
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      "primitive_counts": {
        "pmos": 142,
        "nmos": 142
      },
      "layout_status": "not-generated",
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      "schematic": "schematics/sdm8_output_register.json",
      "spice": "spice/sdm8_output_register.spice",
      "project_bundle": "projects/sdm8_output_register.register.zip"
    },
    {
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      "name": "\u03a3\u0394 \u00b7 CIC2 \u00d7256 \ub514\uc9c0\ud138 \ud544\ud130 \uc804\uccb4",
      "ports": [
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        "RESET",
        "BIT_IN",
        "CODE0",
        "CODE1",
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        "CODE3",
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      ],
      "direct_dependencies": [
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        "SDM8_RESET_SYNC",
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      ],
      "all_child_cells": [
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      ],
      "primitive_counts": {
        "pmos": 2931,
        "nmos": 2931
      },
      "layout_status": "not-generated",
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      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
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      "spice": "spice/sdm8_filter.spice",
      "project_bundle": "projects/sdm8_filter.register.zip"
    },
    {
      "id": "sigma_delta8",
      "name": "\u03a3\u0394 \u00b7 8\ube44\ud2b8 \uc2dc\uadf8\ub9c8\ub378\ud0c0 ADC \u00b7 \uc804\uccb4 \ud558\uc704 \ube14\ub85d",
      "ports": [
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      ],
      "direct_dependencies": [
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      ],
      "all_child_cells": [
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        "SDM8_OTA_FIRST",
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        "PREAMP",
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        "OR2",
        "NOR2",
        "XOR2",
        "DFF_N",
        "SDM8_RESET_SYNC",
        "SDM8_FRAME_COUNTER",
        "SDM8_CIC_INTEGRATORS",
        "SDM8_OUTPUT_REGISTER",
        "SDM8_SCALE_SATURATE"
      ],
      "primitive_counts": {
        "resistor": 7,
        "capacitor": 4,
        "nmos": 2958,
        "pmos": 2955
      },
      "layout_status": "not-generated",
      "physical_verification": "not-run",
      "simulation_scope": "block context; real analog SPICE and/or RTL/gate replay",
      "schematic": "schematics/sigma_delta8.json",
      "spice": "spice/sigma_delta8.spice",
      "project_bundle": "projects/sigma_delta8.register.zip"
    }
  ],
  "foundry_signoff": false
}