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                {
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                "name": "OTA low-frequency gain exceeds 10 V/V",
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    {
      "key": "chip_pll/default",
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    {
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                "pattern": 8,
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    {
      "key": "rc_lowpass/default",
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            "OUT_min": 0,
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              "external_bias_power": "not measured",
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                "available": false,
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    {
      "key": "sar8_analog/default",
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          "message": "Actual Netgen comparison: circuits match uniquely.",
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            "resistors": 20872,
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                      "minimum_current_A": -0.00006170376556392088,
                      "average_power_W": -2.0310914705972165e-8,
                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
                    }
                  },
                  "conversion": {
                    "supply_current": {
                      "available": true,
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                      "minimum_current_A": -0.00005480047506176123,
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
                    },
                    "reference_current": {
                      "available": true,
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                      "average_power_W": 0.0000076229848877932316,
                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                  }
                },
                {
                  "frame": 8,
                  "input_V": 0.8976562499999999,
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                    "supply_current": {
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                    "reference_current": {
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                    "supply_current": {
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                    "reference_current": {
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                {
                  "frame": 9,
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                    "supply_current": {
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                {
                  "frame": 10,
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                    "supply_current": {
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              ],
              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
              "includes": [
                "VDD",
                "VREF"
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              "excludes": [
                "VIN",
                "VCM",
                "BIAS",
                "external control-driver sources",
                "digital controller transistor power"
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              "complete_system_energy": false,
              "Walden_FoM": null,
              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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              "TOP_tail": {
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                "integral": 0.00004117635396893612,
                "mean": 0.8235270793787225,
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          },
          "verification": {
            "schema_version": 1,
            "kind": "sar8_analog",
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            "checks": [
              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
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              {
                "name": "Directed input codes within one LSB",
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                "frame": 0,
                "input_V": 0.6,
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                "error_codes": 0
              },
              {
                "frame": 1,
                "input_V": 0,
                "code": 0,
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              {
                "frame": 2,
                "input_V": 1.2,
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                "error_codes": 0
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              {
                "frame": 3,
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                "error_codes": 1
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              {
                "frame": 4,
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              {
                "frame": 5,
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                "error_codes": 1
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              {
                "frame": 6,
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                "error_codes": 1
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              {
                "frame": 7,
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              {
                "frame": 8,
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                "error_codes": 1
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              {
                "frame": 9,
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                "error_codes": 1
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              {
                "frame": 10,
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            "ambiguous_decisions": 0,
            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
            "gate_sha256": "87a98f9a2f8f3d78b7ba37adbde5a8754c0c9064b7fc2b27c0f20983a7f8e662",
            "scope": "Static directed inputs / optional all 256 bin centers; ±1 code criterion. Not full INL/DNL, noise, ENOB, yield, digital transistor timing or manufacturing signoff.",
            "pass": true
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          "parasitics": {
            "resistors": 20872,
            "capacitors": 8068
          }
        },
        {
          "id": "sar8_analog",
          "key": "sar8_analog/default",
          "stage": "pre",
          "project_id": "db7c2cc30c384efebfc0c10023ce1929",
          "run_id": "0e7e0f993ab44bf7896e16d060985b65",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
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            "analysis": "tran",
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            "x_label": "time",
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                    "supply_current": {
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                  }
                },
                {
                  "frame": 5,
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                  },
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                    "supply_current": {
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                    "reference_current": {
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                      "minimum_current_A": -0.000002430886349858298,
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
                    }
                  }
                },
                {
                  "frame": 6,
                  "input_V": 0.59765625,
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                    "supply_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
                      "available": true,
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                  },
                  "conversion": {
                    "supply_current": {
                      "available": true,
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                      "energy_J": 5.06962960117008e-10,
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                  }
                },
                {
                  "frame": 7,
                  "input_V": 0.60234375,
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                    "supply_current": {
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                    "reference_current": {
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                    "supply_current": {
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                    "reference_current": {
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                },
                {
                  "frame": 8,
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                {
                  "frame": 9,
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                {
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              ],
              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
              "includes": [
                "VDD",
                "VREF"
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              "excludes": [
                "VIN",
                "VCM",
                "BIAS",
                "external control-driver sources",
                "digital controller transistor power"
              ],
              "complete_system_energy": false,
              "Walden_FoM": null,
              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
              },
              "TOP_tail": {
                "available": true,
                "start": 0.00015000000000000001,
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                "integral": 0.00003985541995984973,
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                "method": "Exact moments of piecewise-linear samples with interpolated boundaries; adaptive-step weighted."
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          },
          "verification": {
            "schema_version": 1,
            "kind": "sar8_analog",
            "source": "continuous ngspice MOS/capacitor decisions + actual Icarus RTL/gate/CMOS replay",
            "checks": [
              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
              },
              {
                "name": "Directed input codes within one LSB",
                "pass": true
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            ],
            "frames": [
              {
                "frame": 0,
                "input_V": 0.6,
                "code": 128,
                "expected_code": 128,
                "error_codes": 0
              },
              {
                "frame": 1,
                "input_V": 0,
                "code": 0,
                "expected_code": 0,
                "error_codes": 0
              },
              {
                "frame": 2,
                "input_V": 1.2,
                "code": 255,
                "expected_code": 255,
                "error_codes": 0
              },
              {
                "frame": 3,
                "input_V": 0.00234375,
                "code": 0,
                "expected_code": 0,
                "error_codes": 0
              },
              {
                "frame": 4,
                "input_V": 0.007031249999999999,
                "code": 1,
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                "error_codes": 0
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              {
                "frame": 5,
                "input_V": 0.29765625,
                "code": 63,
                "expected_code": 63,
                "error_codes": 0
              },
              {
                "frame": 6,
                "input_V": 0.59765625,
                "code": 127,
                "expected_code": 127,
                "error_codes": 0
              },
              {
                "frame": 7,
                "input_V": 0.60234375,
                "code": 128,
                "expected_code": 128,
                "error_codes": 0
              },
              {
                "frame": 8,
                "input_V": 0.8976562499999999,
                "code": 191,
                "expected_code": 191,
                "error_codes": 0
              },
              {
                "frame": 9,
                "input_V": 1.19296875,
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                "error_codes": 0
              },
              {
                "frame": 10,
                "input_V": 1.1976562499999999,
                "code": 255,
                "expected_code": 255,
                "error_codes": 0
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            "ambiguous_decisions": 0,
            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
            "gate_sha256": "87a98f9a2f8f3d78b7ba37adbde5a8754c0c9064b7fc2b27c0f20983a7f8e662",
            "scope": "Static directed inputs / optional all 256 bin centers; ±1 code criterion. Not full INL/DNL, noise, ENOB, yield, digital transistor timing or manufacturing signoff.",
            "pass": true
          }
        }
      ]
    },
    {
      "key": "sar8_bottom_switch/default",
      "id": "sar8_bottom_switch",
      "project_id": "8938af97ca99483ab3a41cd12a14a897",
      "stages": [
        {
          "id": "sar8_bottom_switch",
          "key": "sar8_bottom_switch/default",
          "stage": "pre",
          "project_id": "8938af97ca99483ab3a41cd12a14a897",
          "run_id": "0c0809c3aa1c4306a6f5acce69a2c3fd",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
          "message": "Actual charge-retaining SAR comparator decisions and RTL/gate replay completed.",
          "elapsed_s": 11.191233793040738,
          "measurements": {
            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
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            "frames": 11,
            "max_code_error": 0,
            "ambiguous_decisions": 0,
            "rtl_gate_replay_match": true,
            "lsb_V": 0.0046875,
            "conversion_s": 0.000018,
            "effective_resolution": "not measured",
            "source_energy": {
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                    "reference_current": {
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                    "supply_current": {
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                  "frame": 9,
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              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
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              "excludes": [
                "VIN",
                "VCM",
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                "external control-driver sources",
                "digital controller transistor power"
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              "complete_system_energy": false,
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              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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              "external_bias_power": "not measured",
              "complete_system_power_available": false,
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                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
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              {
                "name": "Comparator logic levels unambiguous at decision edges",
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              {
                "name": "Directed input codes within one LSB",
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                "frame": 3,
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                "frame": 6,
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    },
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      "key": "sar8_comparator/default",
      "id": "sar8_comparator",
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                    "supply_current": {
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                    "reference_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                  }
                },
                {
                  "frame": 6,
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                    "supply_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
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                  },
                  "conversion": {
                    "supply_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                },
                {
                  "frame": 7,
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                    "supply_current": {
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                },
                {
                  "frame": 8,
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                {
                  "frame": 9,
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                {
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              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
              "includes": [
                "VDD",
                "VREF"
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              "excludes": [
                "VIN",
                "VCM",
                "BIAS",
                "external control-driver sources",
                "digital controller transistor power"
              ],
              "complete_system_energy": false,
              "Walden_FoM": null,
              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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                "integral": 0.00003985624430919912,
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          },
          "verification": {
            "schema_version": 1,
            "kind": "sar8_comparator",
            "source": "continuous ngspice MOS/capacitor decisions + actual Icarus RTL/gate/CMOS replay",
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              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
              },
              {
                "name": "Directed input codes within one LSB",
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            ],
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                "frame": 0,
                "input_V": 0.6,
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                "expected_code": 128,
                "error_codes": 0
              },
              {
                "frame": 1,
                "input_V": 0,
                "code": 0,
                "expected_code": 0,
                "error_codes": 0
              },
              {
                "frame": 2,
                "input_V": 1.2,
                "code": 255,
                "expected_code": 255,
                "error_codes": 0
              },
              {
                "frame": 3,
                "input_V": 0.00234375,
                "code": 0,
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                "error_codes": 0
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              {
                "frame": 4,
                "input_V": 0.007031249999999999,
                "code": 1,
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                "error_codes": 0
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              {
                "frame": 5,
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                "code": 63,
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                "error_codes": 0
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              {
                "frame": 6,
                "input_V": 0.59765625,
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                "error_codes": 0
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              {
                "frame": 7,
                "input_V": 0.60234375,
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                "expected_code": 128,
                "error_codes": 0
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              {
                "frame": 8,
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                "error_codes": 0
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              {
                "frame": 9,
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                "error_codes": 0
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              {
                "frame": 10,
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            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
            "gate_sha256": "87a98f9a2f8f3d78b7ba37adbde5a8754c0c9064b7fc2b27c0f20983a7f8e662",
            "scope": "Static directed inputs / optional all 256 bin centers; ±1 code criterion. Not full INL/DNL, noise, ENOB, yield, digital transistor timing or manufacturing signoff.",
            "pass": true
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        }
      ]
    },
    {
      "key": "sar8_controller/default",
      "id": "sar8_controller",
      "project_id": "d3640911821f4140810c4b2d49d4ffa8",
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        {
          "id": "sar8_controller",
          "key": "sar8_controller/default",
          "stage": "pre",
          "project_id": "d3640911821f4140810c4b2d49d4ffa8",
          "run_id": "e52dbfcd6d284a8abd59c9ea72b0f5c5",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
          "message": "Actual charge-retaining SAR comparator decisions and RTL/gate replay completed.",
          "elapsed_s": 8.20852221106179,
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            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
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            "ambiguous_decisions": 0,
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            "conversion_s": 0.000018,
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
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                    "supply_current": {
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                    "reference_current": {
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                },
                {
                  "frame": 10,
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                    "supply_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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              ],
              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
              "includes": [
                "VDD",
                "VREF"
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              "excludes": [
                "VIN",
                "VCM",
                "BIAS",
                "external control-driver sources",
                "digital controller transistor power"
              ],
              "complete_system_energy": false,
              "Walden_FoM": null,
              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": true,
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                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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                "integral": 0.00003985624430919912,
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          },
          "verification": {
            "schema_version": 1,
            "kind": "sar8_switch",
            "source": "continuous ngspice MOS/capacitor decisions + actual Icarus RTL/gate/CMOS replay",
            "checks": [
              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
              },
              {
                "name": "Directed input codes within one LSB",
                "pass": true
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                "frame": 0,
                "input_V": 0.6,
                "code": 128,
                "expected_code": 128,
                "error_codes": 0
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              {
                "frame": 1,
                "input_V": 0,
                "code": 0,
                "expected_code": 0,
                "error_codes": 0
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              {
                "frame": 2,
                "input_V": 1.2,
                "code": 255,
                "expected_code": 255,
                "error_codes": 0
              },
              {
                "frame": 3,
                "input_V": 0.00234375,
                "code": 0,
                "expected_code": 0,
                "error_codes": 0
              },
              {
                "frame": 4,
                "input_V": 0.007031249999999999,
                "code": 1,
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                "error_codes": 0
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              {
                "frame": 5,
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                "code": 63,
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                "error_codes": 0
              },
              {
                "frame": 6,
                "input_V": 0.59765625,
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                "error_codes": 0
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              {
                "frame": 7,
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                "error_codes": 0
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              {
                "frame": 8,
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                "error_codes": 0
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              {
                "frame": 9,
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                "error_codes": 0
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              {
                "frame": 10,
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            "ambiguous_decisions": 0,
            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
            "gate_sha256": "87a98f9a2f8f3d78b7ba37adbde5a8754c0c9064b7fc2b27c0f20983a7f8e662",
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            "pass": true
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        }
      ]
    },
    {
      "key": "sar8_unit_cap/default",
      "id": "sar8_unit_cap",
      "project_id": "9df8d2ea151146518d988c21c7cf3a7f",
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        {
          "id": "sar8_unit_cap",
          "key": "sar8_unit_cap/default",
          "stage": "pre",
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          "run_id": "39b75a45a5de400caaf20ac455981dc5",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
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                  }
                },
                {
                  "frame": 6,
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                    "supply_current": {
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
                    },
                    "reference_current": {
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                    }
                  },
                  "conversion": {
                    "supply_current": {
                      "available": true,
                      "start_s": 0.00010999999999999999,
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                      "energy_J": 5.067523982767052e-10,
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                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
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                    "reference_current": {
                      "available": true,
                      "start_s": 0.00010999999999999999,
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                      "energy_J": 1.0147853683535633e-10,
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                      "average_power_W": 0.000006342408552209767,
                      "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD"
                    }
                  }
                },
                {
                  "frame": 7,
                  "input_V": 0.60234375,
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                    "supply_current": {
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                    "reference_current": {
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                    "supply_current": {
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                },
                {
                  "frame": 8,
                  "input_V": 0.8976562499999999,
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                    "reference_current": {
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                    "supply_current": {
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                {
                  "frame": 9,
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                {
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              ],
              "convention": "signed source work integral V*(-i(source))*dt; negative means energy returned to that source",
              "includes": [
                "VDD",
                "VREF"
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              "excludes": [
                "VIN",
                "VCM",
                "BIAS",
                "external control-driver sources",
                "digital controller transistor power"
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              "complete_system_energy": false,
              "Walden_FoM": null,
              "scope": "Acquisition includes reset/recharge; startup-dependent directed conversions, not stationary ADC FoM or paper replication."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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          },
          "verification": {
            "schema_version": 1,
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            "checks": [
              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
              },
              {
                "name": "Directed input codes within one LSB",
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                "expected_code": 128,
                "error_codes": 0
              },
              {
                "frame": 1,
                "input_V": 0,
                "code": 0,
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              {
                "frame": 2,
                "input_V": 1.2,
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                "error_codes": 0
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              {
                "frame": 3,
                "input_V": 0.00234375,
                "code": 0,
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                "error_codes": 0
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              {
                "frame": 4,
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              {
                "frame": 5,
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                "error_codes": 0
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              {
                "frame": 6,
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                "error_codes": 0
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              {
                "frame": 7,
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                "error_codes": 0
              },
              {
                "frame": 8,
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              {
                "frame": 9,
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                "error_codes": 0
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              {
                "frame": 10,
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            "ambiguous_decisions": 0,
            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
            "gate_sha256": "87a98f9a2f8f3d78b7ba37adbde5a8754c0c9064b7fc2b27c0f20983a7f8e662",
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            "pass": true
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      ]
    },
    {
      "key": "sar_adc8/default",
      "id": "sar_adc8",
      "project_id": "e5867cf4fdd34df094982b0d15a006c6",
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        {
          "id": "sar_adc8",
          "key": "sar_adc8/default",
          "stage": "pre",
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          "run_id": "ac37ce556b784e0e86cf445088a8c0d4",
          "revision": 1,
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          "freshness": "current",
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            "scope": "Static directed inputs / optional all 256 bin centers; ±1 code criterion. Not full INL/DNL, noise, ENOB, yield, digital transistor timing or manufacturing signoff.",
            "pass": true
          }
        }
      ]
    },
    {
      "key": "sdm8_bias/default",
      "id": "sdm8_bias",
      "project_id": "f4d9014f1cdc4526b70f3502f72bd3be",
      "stages": [
        {
          "id": "sdm8_bias",
          "key": "sdm8_bias/default",
          "stage": "pre",
          "project_id": "f4d9014f1cdc4526b70f3502f72bd3be",
          "run_id": "52906c5003764f9b98f3391b3746a2cb",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
          "message": "Actual SPICE/RTL ADC co-simulation (sdm8_bias): 16481 analog samples, 8 output words; ENOB measured only for a coherent sine record.",
          "elapsed_s": 86.06698138907086,
          "measurements": {
            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
            "supply_V": 1.8,
            "corner": "tt",
            "temperature_C": 27,
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            "sampled_bits": 2059,
            "decimated_frames": 8,
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            "output_rate_Hz": 3906.25,
            "output_LSB_V": 0.00703125,
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            "cosimulation": "actual ngspice + Icarus RTL + synthesized gates",
            "current_flow_status": "supply-only; internal device-current overlay not computed",
            "ENOB_bits": null,
            "ENOB_status": "not measured by a DC run; code width is not effective resolution",
            "block_context": "sdm8_bias",
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              "group_delay_s": 0.000255,
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
            },
            "analog_supply_energy": {
              "available": true,
              "start_s": 0,
              "end_s": 0.002059999999999,
              "energy_J": 2.207867271744889e-7,
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              "peak_current_A": 0.03419762257296,
              "minimum_current_A": 0.0000168837137679,
              "average_power_W": 0.00010717802290028937,
              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": true,
                "start_s": 0,
                "end_s": 0.002059999999999,
                "energy_J": 2.329605277236985e-7,
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                "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
              },
              "INT_OUT_tail": {
                "available": true,
                "start": 0.00154499999999925,
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                "method": "Exact moments of piecewise-linear samples with interpolated boundaries; adaptive-step weighted."
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            }
          },
          "verification": {
            "schema_version": 1,
            "kind": "sdm8_bias",
            "source": "actual ngspice transistor samples → Icarus RTL and gate replay",
            "scope": "Nominal deterministic conversion and digital consistency; not ENOB8, physical or foundry signoff.",
            "pass": true,
            "checks": [
              {
                "name": "RTL / synthesized gates / independent integer oracle match",
                "observed": 1,
                "pass": true
              },
              {
                "name": "No ambiguous sampled analog logic levels",
                "observed": 0,
                "pass": true
              },
              {
                "name": "Decimated frames after two-frame settling",
                "observed": 6,
                "pass": true
              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
                "observed": 0,
                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_cic_combs/default",
      "id": "sdm8_cic_combs",
      "project_id": "28da3cae3c8141f38c863a589014b9ca",
      "stages": [
        {
          "id": "sdm8_cic_combs",
          "key": "sdm8_cic_combs/default",
          "stage": "pre",
          "project_id": "28da3cae3c8141f38c863a589014b9ca",
          "run_id": "b55714d6c62a4c9a9db582dba7e5fe54",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
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          "message": "Actual Icarus block-context test for sdm8_cic_combs: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
          "elapsed_s": 1.8481477840105072,
          "measurements": {
            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
            "samples": 7252,
            "directed_densities": "0,1,64,128,192,255,256 / 256",
            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
              }
            }
          },
          "verification": {
            "schema_version": 1,
            "kind": "sdm8_cic_combs",
            "source": "actual Icarus RTL and synthesized-gate replay",
            "scope": "Block-context digital functional verification; analog execution and transistor timing not performed.",
            "pass": true,
            "checks": [
              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
                "observed": 7252,
                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_cic_integrators/default",
      "id": "sdm8_cic_integrators",
      "project_id": "d4088394df6b488fadf3b75145662175",
      "stages": [
        {
          "id": "sdm8_cic_integrators",
          "key": "sdm8_cic_integrators/default",
          "stage": "pre",
          "project_id": "d4088394df6b488fadf3b75145662175",
          "run_id": "ed01c4652f4a46e28287e79dea2bd52f",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
          "message": "Actual Icarus block-context test for sdm8_cic_integrators: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
          "elapsed_s": 2.281907896976918,
          "measurements": {
            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
            "samples": 7252,
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            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
              }
            }
          },
          "verification": {
            "schema_version": 1,
            "kind": "sdm8_cic_integrators",
            "source": "actual Icarus RTL and synthesized-gate replay",
            "scope": "Block-context digital functional verification; analog execution and transistor timing not performed.",
            "pass": true,
            "checks": [
              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
                "observed": 7252,
                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_clock_buffer/default",
      "id": "sdm8_clock_buffer",
      "project_id": "b2b002eff7f543049f3c4a04338b14e6",
      "stages": [
        {
          "id": "sdm8_clock_buffer",
          "key": "sdm8_clock_buffer/default",
          "stage": "pre",
          "project_id": "b2b002eff7f543049f3c4a04338b14e6",
          "run_id": "cde0882d43a9429394542af51c2a834c",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
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          "message": "Actual SPICE/RTL ADC co-simulation (sdm8_clock_buffer): 16481 analog samples, 8 output words; ENOB measured only for a coherent sine record.",
          "elapsed_s": 79.39231249107979,
          "measurements": {
            "analysis": "tran",
            "x_unit": "s",
            "x_label": "time",
            "supply_V": 1.8,
            "corner": "tt",
            "temperature_C": 27,
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            "output_rate_Hz": 3906.25,
            "output_LSB_V": 0.00703125,
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            "ambiguous_logic_samples": 0,
            "cosimulation": "actual ngspice + Icarus RTL + synthesized gates",
            "current_flow_status": "supply-only; internal device-current overlay not computed",
            "ENOB_bits": null,
            "ENOB_status": "not measured by a DC run; code width is not effective resolution",
            "block_context": "sdm8_clock_buffer",
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              "dc_gain": 65536,
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
            },
            "analog_supply_energy": {
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              "start_s": 0,
              "end_s": 0.002059999999999,
              "energy_J": 2.207867271744889e-7,
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              "minimum_current_A": 0.0000168837137679,
              "average_power_W": 0.00010717802290028937,
              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": true,
                "start_s": 0,
                "end_s": 0.002059999999999,
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                "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
              },
              "INT_OUT_tail": {
                "available": true,
                "start": 0.00154499999999925,
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            }
          },
          "verification": {
            "schema_version": 1,
            "kind": "sdm8_clock_buffer",
            "source": "actual ngspice transistor samples → Icarus RTL and gate replay",
            "scope": "Nominal deterministic conversion and digital consistency; not ENOB8, physical or foundry signoff.",
            "pass": true,
            "checks": [
              {
                "name": "RTL / synthesized gates / independent integer oracle match",
                "observed": 1,
                "pass": true
              },
              {
                "name": "No ambiguous sampled analog logic levels",
                "observed": 0,
                "pass": true
              },
              {
                "name": "Decimated frames after two-frame settling",
                "observed": 6,
                "pass": true
              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
                "observed": 0,
                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_comparator/default",
      "id": "sdm8_comparator",
      "project_id": "58d00e3c74d440b2b59ae53eb9ee016b",
      "stages": [
        {
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          "stage": "pre",
          "project_id": "58d00e3c74d440b2b59ae53eb9ee016b",
          "run_id": "f987a131e8d048f984c9b7df369a6dff",
          "revision": 1,
          "execution_status": "completed",
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          "message": "Actual SPICE/RTL ADC co-simulation (sdm8_comparator): 16481 analog samples, 8 output words; ENOB measured only for a coherent sine record.",
          "elapsed_s": 85.85571561998222,
          "measurements": {
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            "corner": "tt",
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            "output_rate_Hz": 3906.25,
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            "cosimulation": "actual ngspice + Icarus RTL + synthesized gates",
            "current_flow_status": "supply-only; internal device-current overlay not computed",
            "ENOB_bits": null,
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            "block_context": "sdm8_comparator",
            "cic_response": {
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
            },
            "analog_supply_energy": {
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              "end_s": 0.002059999999999,
              "energy_J": 2.207867271744889e-7,
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": true,
                "start_s": 0,
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                "energy_J": 2.329605277236985e-7,
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                "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
              },
              "INT_OUT_tail": {
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          },
          "verification": {
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            "kind": "sdm8_comparator",
            "source": "actual ngspice transistor samples → Icarus RTL and gate replay",
            "scope": "Nominal deterministic conversion and digital consistency; not ENOB8, physical or foundry signoff.",
            "pass": true,
            "checks": [
              {
                "name": "RTL / synthesized gates / independent integer oracle match",
                "observed": 1,
                "pass": true
              },
              {
                "name": "No ambiguous sampled analog logic levels",
                "observed": 0,
                "pass": true
              },
              {
                "name": "Decimated frames after two-frame settling",
                "observed": 6,
                "pass": true
              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
                "observed": 0,
                "pass": true
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_dac/default",
      "id": "sdm8_dac",
      "project_id": "2c3b45da2053497dbdfd2794292550a9",
      "stages": [
        {
          "id": "sdm8_dac",
          "key": "sdm8_dac/default",
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          "run_id": "81b21e60585c4391992b4099173d6364",
          "revision": 1,
          "execution_status": "completed",
          "analysis_result": "pass",
          "freshness": "current",
          "message": "Actual SPICE/RTL ADC co-simulation (sdm8_dac): 16481 analog samples, 8 output words; ENOB measured only for a coherent sine record.",
          "elapsed_s": 78.72040358302183,
          "measurements": {
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            "output_rate_Hz": 3906.25,
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            "cosimulation": "actual ngspice + Icarus RTL + synthesized gates",
            "current_flow_status": "supply-only; internal device-current overlay not computed",
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            "ENOB_status": "not measured by a DC run; code width is not effective resolution",
            "block_context": "sdm8_dac",
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
            },
            "analog_supply_energy": {
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              "energy_J": 2.207867271744889e-7,
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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              "INT_OUT_tail": {
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          },
          "verification": {
            "schema_version": 1,
            "kind": "sdm8_dac",
            "source": "actual ngspice transistor samples → Icarus RTL and gate replay",
            "scope": "Nominal deterministic conversion and digital consistency; not ENOB8, physical or foundry signoff.",
            "pass": true,
            "checks": [
              {
                "name": "RTL / synthesized gates / independent integer oracle match",
                "observed": 1,
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              },
              {
                "name": "No ambiguous sampled analog logic levels",
                "observed": 0,
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              {
                "name": "Decimated frames after two-frame settling",
                "observed": 6,
                "pass": true
              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
                "observed": 0,
                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_filter/default",
      "id": "sdm8_filter",
      "project_id": "729ecb4d4c5e4dab9e55e2e26713bbda",
      "stages": [
        {
          "id": "sdm8_filter",
          "key": "sdm8_filter/default",
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          "revision": 1,
          "execution_status": "completed",
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          "message": "Actual Icarus block-context test for sdm8_filter: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
          "elapsed_s": 2.478331294027157,
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            "analysis": "tran",
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            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
              }
            }
          },
          "verification": {
            "schema_version": 1,
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            "pass": true,
            "checks": [
              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
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                "pass": true
              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_frame_counter/default",
      "id": "sdm8_frame_counter",
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      "stages": [
        {
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          "message": "Actual Icarus block-context test for sdm8_frame_counter: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
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            "analysis": "tran",
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            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
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            }
          },
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            "schema_version": 1,
            "kind": "sdm8_frame_counter",
            "source": "actual Icarus RTL and synthesized-gate replay",
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            "pass": true,
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              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_input_filter/default",
      "id": "sdm8_input_filter",
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      "stages": [
        {
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          "key": "sdm8_input_filter/default",
          "stage": "pre",
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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          },
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              {
                "name": "No ambiguous sampled analog logic levels",
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              {
                "name": "Decimated frames after two-frame settling",
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              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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              }
            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_integrator/default",
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        {
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
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              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
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              {
                "name": "Decimated frames after two-frame settling",
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              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_modulator/default",
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      "stages": [
        {
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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    },
    {
      "key": "sdm8_ota/default",
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
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          },
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              {
                "name": "Decimated frames after two-frame settling",
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                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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    },
    {
      "key": "sdm8_output_register/default",
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        {
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          "message": "Actual Icarus block-context test for sdm8_output_register: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
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            "analog_execution": "not performed for digital standalone blocks",
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              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
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            }
          },
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              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_reference/default",
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        {
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          "revision": 1,
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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              {
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              {
                "name": "No ambiguous sampled analog logic levels",
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              {
                "name": "Decimated frames after two-frame settling",
                "observed": 6,
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              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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                "pass": true
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_reset_switch/default",
      "id": "sdm8_reset_switch",
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        {
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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            "analog_supply_energy": {
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
              "input_drivers_power": "not measured",
              "external_bias_power": "not measured",
              "complete_system_power_available": false,
              "supply": {
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                "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
                "sample_scope": "Integration of the returned trace; ADC raw-source energy is reported separately before display thinning."
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              "INT_OUT_tail": {
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          },
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            "schema_version": 1,
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            "pass": true,
            "checks": [
              {
                "name": "RTL / synthesized gates / independent integer oracle match",
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              {
                "name": "No ambiguous sampled analog logic levels",
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              {
                "name": "Decimated frames after two-frame settling",
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              },
              {
                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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                "pass": true
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            ]
          }
        }
      ]
    },
    {
      "key": "sdm8_reset_sync/default",
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        {
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            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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              "supply": {
                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
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            }
          },
          "verification": {
            "schema_version": 1,
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            "pass": true,
            "checks": [
              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
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    },
    {
      "key": "sdm8_sample_latch/default",
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      "stages": [
        {
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              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
            },
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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                "name": "No ambiguous sampled analog logic levels",
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                "name": "Decimated frames after two-frame settling",
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    },
    {
      "key": "sdm8_scale_saturate/default",
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          "message": "Actual Icarus block-context test for sdm8_scale_saturate: 7252 clocks, RTL and synthesized gates; no analog execution claim.",
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            "cosimulation": "RTL / synthesized gates / integer reference",
            "analog_execution": "not performed for digital standalone blocks",
            "research_metrics": {
              "source": "returned native trace samples, possibly display-thinned; source coverage is explicit",
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                "available": false,
                "reason": "No analog supply-current trace; RTL/gate replay is not transistor power."
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          },
          "verification": {
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            "pass": true,
            "checks": [
              {
                "name": "Every clock matches independent modulo-CIC oracle, including reset and saturation",
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      "key": "sigma_delta8/default",
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      "stages": [
        {
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              "formula": "|sin(pi*f*R/Fs)/(R*sin(pi*f/Fs))|^N",
              "source": "independent mathematical CIC response, not a measured analog transfer or ENOB"
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              "source": "actual -i(VDD), signed trapezoidal integration; constant testbench VDD",
              "scope": "All raw analog samples before display thinning; excludes digital RTL and external input/clock/reset power."
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              {
                "name": "RTL / synthesized gates / independent integer oracle match",
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              {
                "name": "No ambiguous sampled analog logic levels",
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                "name": "Decimated frames after two-frame settling",
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                "name": "Nominal DC conversion error ≤ 2 LSB (not ENOB)",
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    {
      "key": "soc_cascode_mirror/default",
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    {
      "key": "soc_filter2/default",
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                "name": "measured finite bandwidth",
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            "scope": "Actual SKY130 analog macro; nominal directed criteria only; no noise/mismatch/ESD/EM/IR/foundry signoff.",
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    {
      "key": "soc_miller_ota/default",
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        {
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    {
      "key": "soc_miller_ota/nulling-15000",
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}