{
  "schema_version": 1,
  "reviewed_at": "2026-10-13",
  "scope": "Selected accessible primary sources, 2025–2026 plus one explicitly dated layout foundation. This is not an exhaustive systematic review.",
  "papers": [
    {
      "id": "ez130-2026",
      "title": "An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students",
      "authors": "Oscar Castañeda et al.",
      "date": "2026-09-24",
      "venue": "arXiv preprint v1",
      "doi": "10.48550/arXiv.2609.29965",
      "url": "https://arxiv.org/abs/2609.29965",
      "read_scope": "Full HTML, sections II-C, III-A–III-D",
      "technology": "IHP SG13G2, not SKY130",
      "adopted": "Drive-strength exploration and separate functional, timing, energy and physical evidence.",
      "not_reproduced": "EZ130 cells, LEF/Liberty interfaces, published PPA and silicon results."
    },
    {
      "id": "zlibboost-2026",
      "title": "ZlibBoost: An Efficient and Flexible Open-Source Framework for Standard Cell Characterization",
      "authors": "Zhengrui Chen et al.",
      "date": "2026-03-19",
      "venue": "ACM TODAES 31(4), article 74; accepted manuscript online 2025-07-02",
      "doi": "10.1145/3747182",
      "url": "https://doi.org/10.1145/3747182",
      "read_scope": "Publisher indexed abstract and NLDM section; author repository README. Full publisher page access failed.",
      "technology": "Characterization methodology; paper benchmarks include commercial 65 nm",
      "adopted": "Sensitized single-input timing arcs, explicit slew/load conditions and measured tables.",
      "not_reproduced": "ZlibBoost implementation, ML interpolation, complete NLDM/Liberty, hidden power and sequential timing models."
    },
    {
      "id": "sar-reset-2025",
      "title": "A 2.8 fJ/conversion-step 10-bit 500 kS/s SAR ADC with low-power switching scheme and dynamic comparator",
      "authors": "Linlin Huang; Jianhui Wu",
      "date": "2025-01-10",
      "venue": "IEICE Electronics Express 22(1), 20240528",
      "doi": "10.1587/elex.21.20240528",
      "url": "https://www.jstage.jst.go.jp/article/elex/22/1/22_21.20240528/_article",
      "read_scope": "Full PDF, sections 2.2–2.4 and 3",
      "technology": "40 nm CMOS, differential 10-bit ADC, 0.7 V",
      "adopted": "Separate acquisition/reset, conversion, VDD and reference-source signed energy; no omitted reset-energy claim.",
      "not_reproduced": "Differential switching topology, bootstrap/double-tail comparator or published energy, ENOB and capacitor reduction. Existing single-ended SKY130 ADC is preserved."
    },
    {
      "id": "sdm-cic-2025",
      "title": "Design of low power energy efficient sigma-delta ADC for biomedical IoT applications",
      "authors": "Buddhi Prakash Sharma; Anu Gupta; Chandra Shekhar; Raman Chauhan; Vinay Chamola",
      "date": "2025",
      "venue": "Scientific Reports 15, 36165",
      "doi": "10.1038/s41598-025-19272-4",
      "url": "https://www.nature.com/articles/s41598-025-19272-4",
      "read_scope": "Full publisher PDF, proposed digital filter and CIC design sections",
      "technology": "SCL 180 nm, 14-bit output; not SKY130",
      "adopted": "Review existing CIC2 hierarchy; expose independently derived normalized response, droop, DC gain and group delay.",
      "not_reproduced": "14 ENOB, folded-cascode implementation, counter power savings or reported silicon performance. Paper SNR expressions are not used as a substitute for actual FFT results."
    },
    {
      "id": "ldo-psrr-2025",
      "title": "A Wide-Input 0.25 um BCD LDO with Dual-Stage Amplifier and Active Ripple Cancellation for High PSRR and Fast Transient Response",
      "authors": "Yi Zhang; Zhuolong Chen; Zhenghao Xu; Yujin He",
      "date": "2025-07-28",
      "venue": "arXiv preprint v1; not peer-review certification",
      "doi": "10.48550/arXiv.2507.20522",
      "url": "https://arxiv.org/abs/2507.20522",
      "read_scope": "Full PDF, sections on compensation, PSRR and load transient",
      "technology": "0.25 um BCD, high-voltage LDO; incompatible with SKY130 1.8 V primitives",
      "adopted": "Measure supply-to-output AC transfer and positive rejection convention; make compensation resistance explicit and retain real transient criteria.",
      "not_reproduced": "High-voltage devices, active ripple-cancellation branch, adaptive feedback, published PSRR and recovery performance."
    },
    {
      "id": "clock-gating-2026",
      "title": "Clock-Gating Insertion Strategies on an Open-Source MSP430 Core: A Reproducible PPA Study and a Gate-Level Simulation Caveat",
      "authors": "Xingran Huang; Qiming Guo; Jinwen Tang; Wenqi Jia; Dongzheng Wang",
      "date": "2026-08-31",
      "venue": "arXiv preprint v1; authors report acceptance at IEEE UEMCON 2026",
      "doi": "10.48550/arXiv.2608.30954",
      "url": "https://arxiv.org/abs/2608.30954",
      "read_scope": "Full HTML, sections IV-B–D and V-G",
      "technology": "openMSP430, commercial 32 nm synthesis flow; not this accumulator CPU",
      "adopted": "Keep RTL/gate/CMOS replay and transistor timing as distinct evidence; explicitly report unavailable clock-gating/STA closure.",
      "not_reproduced": "ICG insertion, MSP430 architecture, SDF/STA closure or reported PPA savings."
    },
    {
      "id": "placement-2024",
      "title": "Automated Placement of Analog Integrated Circuits using Priority-based Constructive Heuristic",
      "authors": "Josef Grus; Zdeněk Hanzálek",
      "date": "2024-11-13",
      "venue": "arXiv v2, foundational source rather than latest research",
      "doi": "10.48550/arXiv.2411.02406",
      "url": "https://arxiv.org/abs/2411.02406",
      "read_scope": "Full HTML, sections 3 and 4.1.4",
      "technology": "Analog placement constraints and symmetry groups",
      "adopted": "Audit native matched-unit centroids, preserve indivisible groups and complete chip-envelope constraints.",
      "not_reproduced": "ILP, GA, CMA-ES, DQN or paper placement benchmarks. Equal centroids do not certify identical surroundings or mismatch yield."
    },
    {
      "id": "isscc-trends-2026",
      "title": "ISSCC 2026 Press Kit — Analog, Power Management, Data Converters and Frequency Synthesizers trends",
      "authors": "ISSCC technical subcommittees",
      "date": "2026",
      "venue": "Official conference summaries; not full research papers",
      "doi": null,
      "url": "https://www.isscc.org/s/ISSCC2026PressKit.pdf",
      "read_scope": "PDF pages 97–98 and 113–122 (zero-based), including paper 32.2 summary",
      "technology": "Multiple technologies; architecture and robustness trends only",
      "adopted": "PVT/source-buffer assumptions, source completeness and named noise/linearity/timing gaps on every block.",
      "not_reproduced": "Paper 32.2 dynamic ΔΣ topology, conference circuits, calibration, phase-noise or advertised performance."
    }
  ]
}