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          "stage": "lvs",
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          "run_id": "90a154b5c5e34f55b605149020a1492a",
          "revision": 1,
          "freshness": "current",
          "execution_status": "completed",
          "analysis_result": "pass",
          "message": "Actual Netgen comparison: circuits match uniquely.",
          "elapsed_s": 3.0850278330035508,
          "artifacts": {
            "layout_netlist": "/workspace/.runtime/eda/runs/90a154b5c5e34f55b605149020a1492a/layout.spice",
            "reference_netlist": "/workspace/.runtime/eda/runs/90a154b5c5e34f55b605149020a1492a/reference.spice",
            "lvs_report": "/workspace/.runtime/eda/runs/90a154b5c5e34f55b605149020a1492a/lvs.log",
            "stdout": "/workspace/.runtime/eda/runs/90a154b5c5e34f55b605149020a1492a/stdout.log"
          }
        },
        {
          "reference": "sar8_analog",
          "stage": "pex",
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          "run_id": "da7ecb99687342aa8060b870884e91d8",
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          "freshness": "current",
          "execution_status": "completed",
          "analysis_result": "pass",
          "message": "Actual Magic RC extraction: 20869 resistors, 8066 capacitors. Zero counts reflect native thresholds, not inserted elements.",
          "elapsed_s": 5.3829984000185505,
          "parasitics": {
            "resistors": 20869,
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          "artifacts": {
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            "pex_quality": "/workspace/.runtime/eda/runs/da7ecb99687342aa8060b870884e91d8/pex-quality.json",
            "stdout": "/workspace/.runtime/eda/runs/da7ecb99687342aa8060b870884e91d8/stdout.log"
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        },
        {
          "reference": "sar8_analog",
          "stage": "pre",
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          "run_id": "754be8f8291a49fbb1c896f94c9b4909",
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          "message": "Actual charge-retaining SAR comparator decisions and RTL/gate replay completed.",
          "elapsed_s": 17.761863103020005,
          "measurements": {
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            "rtl_gate_replay_match": true,
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            "checks": [
              {
                "name": "RTL / synthesized gates / CMOS schematic reproduce every native comparator decision and trial",
                "pass": true
              },
              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
              },
              {
                "name": "Directed input codes within one LSB",
                "pass": true
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                "frame": 0,
                "input_V": 0.6,
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              {
                "frame": 1,
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              {
                "frame": 2,
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              {
                "frame": 3,
                "input_V": 0.00234375,
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              {
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                "frame": 6,
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              {
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              {
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                "input_V": 0.8976562499999999,
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                "frame": 9,
                "input_V": 1.19296875,
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                "input_V": 1.1976562499999999,
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            "rtl_sha256": "23111df558a25c974ca6884f1ec654357b427314dd9dc9cfa3a7a35d5e02b899",
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            "pass": true
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          "artifacts": {
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            "gate_replay": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/gate-replay.csv",
            "ir_replay": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/ir-replay.csv",
            "testbench": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/testbench.spice",
            "native_decisions": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/decisions.csv",
            "waveform_data": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/waveform.dat",
            "sar_verification": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/sar-verification.json",
            "stdout": "/workspace/.runtime/eda/runs/754be8f8291a49fbb1c896f94c9b4909/stdout.log"
          }
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        {
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              {
                "name": "Comparator logic levels unambiguous at decision edges",
                "pass": true
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              {
                "name": "Directed input codes within one LSB",
                "pass": true
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            "scope": "Static directed inputs / optional all 256 bin centers; ±1 code criterion. Not full INL/DNL, noise, ENOB, yield, digital transistor timing or manufacturing signoff.",
            "pass": true
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            "pex_quality": "/workspace/.runtime/eda/runs/3668c453c28846e69f9f067c53db0f55/pex-quality.json",
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            "pex_reduction": "/workspace/.runtime/eda/runs/3668c453c28846e69f9f067c53db0f55/pex-reduction.json",
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            "gate_replay": "/workspace/.runtime/eda/runs/3668c453c28846e69f9f067c53db0f55/gate-replay.csv",
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            "sar_verification": "/workspace/.runtime/eda/runs/3668c453c28846e69f9f067c53db0f55/sar-verification.json",
            "stdout": "/workspace/.runtime/eda/runs/3668c453c28846e69f9f067c53db0f55/stdout.log"
          }
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  ]
}
